Scott Howard <scott@hunterlink.net.au> wrote in message news:<1097073294.155252@docbert>...
> Chuck <chuckconkling@yahoo.com> wrote:
> > ROOT[1]: W: u1ctr SysFail reset (7001) was initiated at 20041005 225314
> > Cache memory parity error detected
> >
> > This is leading me to believe that someone powered off the T3 array last
> > night. Can anyone help verify this?
> >
>
> No, it means you've had a cache memory parity error.
> In practice this error is actually wrong - the T3's have ECC memory,
> so this actually means you've had an uncorrectable ECC memory error.
>
> Scott.

Actually the orginal T3's did NOT have ECC memory. ECC memory was not
used until the T3+ (T3B) came out. And the very early T3's had a
batch of out of spec memory chips so not only didn't they have ECC
memory, it had memory that was prone to errors... And when you get a
memory parity error in your cache, instead of writing the corrupt
cache data to disk the T3 simply reboots there by losing your data...
nice... trust me here... i'm speaking from experience... However...
there is a ray of sunshine... Sun replaced all our original
controllers with controllers with improved memory chips (still not
ECC) and we haven't had a problem since... Can't remember how to check
but you should make sure your controller is a least Version K.... or
you can upgrade to a T3+ controller...

hth,
j