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01-16-2008, 01:20 PM
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 chip multithreading on ultrasparc iv Hi, The Ultrasparc IV has 2 Ultrasparc III pipeline cores capable of executing instructions from a separate thread on each core. Does this mean in one clock cycle, instructions from 2 threads can execute on the Ultrasparc IV processor? Does the Ultrasparc IV also maintain architectural states for each thread? Thank You, Tri      |
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01-16-2008, 01:20 PM
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| Re: chip multithreading on ultrasparc iv On Fri, 22 Oct 2004, tri wrote: > The Ultrasparc IV has 2 Ultrasparc III pipeline cores capable of > executing instructions from a separate thread on each core. > > Does this mean in one clock cycle, instructions from 2 threads can > execute on the Ultrasparc IV processor? Yes. Niagra will be able to execute 32 threads simultaneously. > Does the Ultrasparc IV also maintain architectural states for each > thread? Not sure what you're asking here... -- Rich Teer, SCNA, SCSA, author of "Solaris Systems Programming" President, Rite Online Inc. Voice: +1 (250) 979-1638 URL: http://www.rite-group.com/rich |
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01-16-2008, 01:20 PM
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| Re: chip multithreading on ultrasparc iv In article <ec1c3924.0410221022.583112bd@posting.google.com >, tri <tringuyen99@yahoo.com> wrote: >Hi, > >The Ultrasparc IV has 2 Ultrasparc III pipeline cores capable of >executing instructions from a separate thread on each core. Yes. >Does this mean in one clock cycle, instructions from 2 threads can >execute on the Ultrasparc IV processor? Yes, think of it as two UltraSPARC III cpu:s. Each of the UltraSPARC III cores can execute totally independent of the other. >Does the Ultrasparc IV also maintain architectural states for each >thread? Calling it multithreaded is a bit misleading when it is in fact two CPU:s using one socket. The naming was a valiant attempt from Sun to try to make ISV licensing "cheaper" or per socket rather than per CPU. For all other puposes its a SMP on a chip. /Regards Fredrik -- Fredrik Lundholm dol @ ce.chalmers.se |
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01-16-2008, 01:21 PM
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| Re: chip multithreading on ultrasparc iv Rich Teer <rich.teer@rite-group.com> wrote in message news:<Pine.SOL.4.58.0410221129030.17681@zaphod.rit e-group.com>... > On Fri, 22 Oct 2004, tri wrote: > > > The Ultrasparc IV has 2 Ultrasparc III pipeline cores capable of > > executing instructions from a separate thread on each core. > > > > Does this mean in one clock cycle, instructions from 2 threads can > > execute on the Ultrasparc IV processor? > > Yes. Niagra will be able to execute 32 threads simultaneously. Each core can simultaneously exec. instructions from a single. So with two cores, each US-IV device can execute instructions from 2 different threads simultaneously. Niagara does not execute 32 threads simultaneously. Niagara uses Switch on Event MultiThreading also known as SoEMT or CMT (Coarse Multithreading). This is similar to Intel's Montecito, except that Montecito hosts 2 threads per core, whereas Niagara hosts 4. Only one thread can use the core at a time, so a Niagara device, with 8 cores, can only execute instructions from 8 different threads at once. I suspect you were thinking about what would happen if each Niagara core used SMT rather than CMT. > > Does the Ultrasparc IV also maintain architectural states for each > > thread? > > Not sure what you're asking here... There is one thread for each core in the US-IV, so of course it does. US-IV is exactly like a 2P system on a single chip. David Kanter Editor Real World Technologies |
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