SEO

Hello

I have these workstations:


#1:

SPARCstation 20 Model 50
Sun S20,501-2324
Two SBus SCSI DMA "Generic SCSI" SCSI controllers
Two "AMD Lance Am7990" 10-Mb Ethernet network interfaces
GX 8-bit Accelerated Color Graphics [cgsix]
"TI Model 50 SuperSPARC SPARCmodule" 50 MHz CPU
Sun SPARCstation 20 (1 X 390Z50)
socket J0201 has a 16MB SIMM
socket J0301 has a 16MB SIMM
empty sockets: J0303 J0202 J0305 J0203 J0302 J0304
total memory = 32MB

#2:

Sun SPARCStation 20
SuperSPARC 60 MHz
RAM 32 Mb, single SIMM
(dead disk right now, so I can't get more information right now)



Is it possible to

a) Put the 60 MHz CPU on #1 so both CPU's will work (I guess is safer
to put the 60 MHz one on the older motherboard than the reverse)
(according to http://mbus.sunhelp.org/misc/genconf.htm it seems it
should work)

b) Use all the SIMMs on a single SS20 (16+16+32)


?

TIA

--
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application/ms-tnef; cat '%s' > /dev/null / con las puertas abiertas
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In <bjqlr1$aqo$1@localhost.escomposlinux.org> "J.A. Gutierrez" <spd@daphne.cps.unizar.es> writes:
> SPARCstation 20 Model 50
> Sun SPARCstation 20 (1 X 390Z50)
>
> Sun SPARCStation 20
> SuperSPARC 60 MHz
>
> Is it possible to
>
> a) Put the 60 MHz CPU on #1 so both CPU's will work

no. they are two different type of processor modules. modules
with SuperCACHE only work with other modules with SuperCACHE.

> b) Use all the SIMMs on a single SS20 (16+16+32)

that should work.

ultrasparc3@hotmail.com wrote:
: In <bjqlr1$aqo$1@localhost.escomposlinux.org> "J.A. Gutierrez" <spd@daphne.cps.unizar.es> writes:
:> SPARCstation 20 Model 50
:> Sun SPARCstation 20 (1 X 390Z50)
:>
:> Sun SPARCStation 20
:> SuperSPARC 60 MHz

Sun SPARCstation 20 (1 X 390Z55)
SPARCstation 20 Model 61
OpenBoot 2.22
"TI Model 61 SuperSPARC SPARCmodule" 60 MHz CPU
:>
:> Is it possible to
:>
:> a) Put the 60 MHz CPU on #1 so both CPU's will work

: no. they are two different type of processor modules. modules
: with SuperCACHE only work with other modules with SuperCACHE.


So the Model 61 is the one with 1 Mb L2, and the Model 50 has
no L2 cache at all, right?

:> b) Use all the SIMMs on a single SS20 (16+16+32)

: that should work.

ok; thanks a lot...

--
finger spd@shiva.cps.unizar.es for PGP /
..mailcap tip of the day: / La vida es una carcel
application/ms-tnef; cat '%s' > /dev/null / con las puertas abiertas
text/x-vcard; cat '%s' > /dev/null / (A. Calamaro)

In article <bjsn7n$utm$1@localhost.escomposlinux.org>,
J.A. Gutierrez <spd@daphne.cps.unizar.es> wrote:

> So the Model 61 is the one with 1 Mb L2, and the Model 50 has
> no L2 cache at all, right?

Yes. Model 50 = 50MHz and no cache, model 61 = 60MHz and 1MB cache.

390Z50 is the SuperSPARC CPU.
390Z55 is the SuperCache cache controller.

If the SuperSPARC CPU is visible on the MBus (the banner shows 390Z50)
then no cache is present. If the SuperSPARC CPU hides behind the cache
controller (the banner shows 390Z55) then the cache is present.

Go to < http://sunsolve.sun.com/handbook_pub...SPARC_TOC.html >
for more information about the different SuperSPARC modules.

--
Göran Larsson http://www.mitt-eget.com/

In article <bjsn7n$utm$1@localhost.escomposlinux.org>,
J.A. Gutierrez <spd@daphne.cps.unizar.es> wrote:
>
>:> b) Use all the SIMMs on a single SS20 (16+16+32)
>
>: that should work.
>
> ok; thanks a lot...

Be sure to put the largest SIMM in the slot that corresponds to
memory bank 0. (J201, farthest from the front panel).

carl
--
carl lowenstein marine physical lab u.c. san diego
clowenst@ucsd.edu

"J.A. Gutierrez" <spd@daphne.cps.unizar.es> writes:

> #1:
> SPARCstation 20 Model 50
> Sun S20,501-2324
> Two SBus SCSI DMA "Generic SCSI" SCSI controllers
> Two "AMD Lance Am7990" 10-Mb Ethernet network interfaces
> GX 8-bit Accelerated Color Graphics [cgsix]
> "TI Model 50 SuperSPARC SPARCmodule" 50 MHz CPU
> Sun SPARCstation 20 (1 X 390Z50)
> socket J0201 has a 16MB SIMM
> socket J0301 has a 16MB SIMM
> empty sockets: J0303 J0202 J0305 J0203 J0302 J0304
> total memory = 32MB

> #2:
> Sun SPARCStation 20
> SuperSPARC 60 MHz
> RAM 32 Mb, single SIMM
> (dead disk right now, so I can't get more information right now)

> Is it possible to

> a) Put the 60 MHz CPU on #1 so both CPU's will work (I guess is safer
> to put the 60 MHz one on the older motherboard than the reverse)
> (according to http://mbus.sunhelp.org/misc/genconf.htm it seems it
> should work)

You should never, ever combine CPU modules of different speed/type. If you
can, obtain another 50 or 60 MHz module and use them in matched pairs of the
same speed/type.

> b) Use all the SIMMs on a single SS20 (16+16+32)

Yes that'll be fine. However, SS20's work best with 32 MB and 64 MB modules
only. Sun's 501-2622 and 501-2480 modules (or 3rd-party equivalents) are
what you should look for.

The newer 128 and 256 MB 200 pin RAM modules while having the exact same
configuration connection-wise are not supported in SS20's.

Regards,

Craig.
--
SUN RIPENED KERNELS - Surplus Sun Microsystems Equipment, Parts + Accessories
Waterfall, NSW, Australia - Operated by Craig Dewick - Founded in 1996
Main site: www.sunrk.com.au - Ebay Shop: www.ebayshops.com.au/sunripenedkernels
Ph: +612-9520-2547 - Fax: +612-9520-2557 - Mobile: 04-2163-0547 (int. +614)

Kralizec Craig <cd@lios.apana.org.au> probably said:
>You should never, ever combine CPU modules of different
>speed/type. If you can, obtain another 50 or 60 MHz module and use
>them in matched pairs of the same speed/type.

While this is what sun will tell you ("Mixing different CPU modules is
not supported") in practice you can mix CPU speeds in SS10s and SS20s.

MBUS modules will coexist at different speeds as long as the MBUS
speed is the same between the two modules, if the modules don't have
cache this means they run at the same CPU speed, if they do have cache
(SMx1 modules) then the bus speed is independant of the processor
speed and they can be mixed if the bus speed is the same.

I've seen SM51s and SM61s mixed quite happily (and still are, that
machine is still running) for a long time in an SS10 and tested
briefly other combinations in SS20s.

The only real negative aspect of doing this is that Solaris assumes
all processors are equal for purposes of scheduling, so CPU scheduling
priorities may be slightly sub-optimal.

P.

--
pir

In aus.computers.sun Kralizec Craig <cd@lios.apana.org.au> wrote:
> "J.A. Gutierrez" <spd@daphne.cps.unizar.es> writes:

>> Is it possible to

>> a) Put the 60 MHz CPU on #1 so both CPU's will work (I guess is safer
>> to put the 60 MHz one on the older motherboard than the reverse)
>> (according to http://mbus.sunhelp.org/misc/genconf.htm it seems it
>> should work)

> You should never, ever combine CPU modules of different speed/type. If you
> can, obtain another 50 or 60 MHz module and use them in matched pairs of the
> same speed/type.

This is wrong.

I safely and happily run an SS20 with a 75MHz and 85MHz CPU inside.

Darren

In <3f7a929a@clarion.carno.net.au> Darren Reed <avalon@caligula.anu.edu.au> writes:
>> You should never, ever combine CPU modules of different speed/type. If you
>> can, obtain another 50 or 60 MHz module and use them in matched pairs of the
>> same speed/type.
>
>This is wrong.

it is actually a very sane guideline.

>I safely and happily run an SS20 with a 75MHz and 85MHz CPU inside.

you are claiming that just because one particular unsupported
configuration appears to work that the general case must also
work? you have never seen ipfilter run just fine in one
environment but cause panics in another depending on NIC
type, rulesets, and network load?

you are happy because those were the last of the SuperSPARC
family and did not require much in the way of operating system
hand-holding. in other words, it is the best-case scenario
for the unsupported mixing of SuperSPARC modules.

30$12$f3i99le@pir.net (Peter Radcliffe) writes:

>Kralizec Craig <cd@lios.apana.org.au> probably said:
>>You should never, ever combine CPU modules of different
>>speed/type. If you can, obtain another 50 or 60 MHz module and use
>>them in matched pairs of the same speed/type.

>While this is what sun will tell you ("Mixing different CPU modules is
>not supported") in practice you can mix CPU speeds in SS10s and SS20s.

>MBUS modules will coexist at different speeds as long as the MBUS
>speed is the same between the two modules, if the modules don't have
>cache this means they run at the same CPU speed, if they do have cache
>(SMx1 modules) then the bus speed is independant of the processor
>speed and they can be mixed if the bus speed is the same.

Now you've said this I do remember reading about it somewhere else in the
past. 8-) It's true that there can be scheduling problems with CPU's of
different master clock rates, but if the Mbus speed of each processor is
matched they will work together electrically on the same system board.

>The only real negative aspect of doing this is that Solaris assumes
>all processors are equal for purposes of scheduling, so CPU scheduling
>priorities may be slightly sub-optimal.

Perhaps there is a way to tweak the way each CPU is indexed for scheduling
purposes but it would not be a very good idea to be fiddling with timing
factors in software as the complexity of the kernel code would no doubt
increase significantly.

Craig.
--
Guru Will Sellit! ** 'sunrk' on Ebay ** | Get Back on Track at the Sun Shack
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Main info website at www.one4sun.org +-------------------------------------
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